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Previous editions
Focus
3-D ICs enable dramatically improved performances at a much lower cost than new leading-edge CMOS technology below 32 nm transistor fabrication. The success of these new ICs depends on the availability of new methodologies and skills that are required to achieve acceptable design quality and productivity. This workshop brings together key actors from semiconductor companies, system design houses and EDA industry to build a vision of the next step in 3D integrated ICs design. Topics addressed are: Applications requiring 3D, interconnect architectures and thermal management for 3D ICs, application partitioning, floorplanning for 3D architectures, modeling, characterization and testing for 3D ICs.
Content
Presentations are not available yet
Download the program here



Registration
Registration is open until 20th of June
Go to Registration



Organization Committee

Co-general Chairs:
Andreas Burg, EPFL
Gilles Poupon, CEA-LETI

Co-program Chairs:
Marc Belleville, CEA-LETI
Jungsoo Kim, EPFL
Georgios Karakonstantis, EPFL

Tutorials Chairs:
Vassileios Pavlidis, EPFL
Fabien Clermidy, CEA-LETI



Organisation Chairs:
Ahmed Jerraya, CEA-LETI
Giovanni De Micheli, EPFL
David Atienza, EPFL

Finance Chair:
Homeira Salimi, EPFL

Website Chair:
Rodolphe Buret, EPFL




Final Program
Day 1: June 25th
8:30-9:00
9:00-10:00




10:00-10:15
10:15-12:15








12:15-13:30
13:30-14:30



14:30-14:45
14:45-16:45











16:45-18:15








19:00




Registration and Opening
Keynote session 1
Toward Five-Dimensional Scaling: How Density Improves Efficiency in Future Computers, Bruno Michel, IBM Zurich, Switzerland
Break
Session 1: Wide I/O and Computing
Vincent Guerin,STE

3D Integration from WideIO Implementation to Computing Perspectives, Denis Dutoit, LETI, Grenoble, France

Co-optimization potential of WIDEIO/DRAMs and Controller, Christian Weis, Univ. of Kaiserslautern, Germany

Steve Lin, UCSD, USA
Lunch
Keynote Session 2
"Going 3D by Evolution rather than by Revolution, Steve Smith, Synopsys, USA
Coffee break
Session 2: Reliability and Thermal Cooling
Overview of Enabling Technologies for Liquid-Cooled 3D Stacks, Yusuf Leblebici, EPFL, Switzerland

Thermal Balancing of Liquid-Cooled 3D-MPSoCs Using Channel Modulation, Mohamed Sabry, EPFL, Switzerland

CMOSAIC 3D Thermal Test Vehicle Design and Fabrication, Yassir Madhour, IBM Zurich, Swizerland

Dimos Poulikakos, ETHZ, Switzerland

Session 3: 3-D Innovation
Interactive field-directed floorplan prototyping for 2D/3D IC's, Antonis Papanikolau, NTUA, Greece

"Reliability Modeling and Design Issues for TSV-based 3D Integration", David Pan, University of Texas, Austin, USA

Chip-Scale Silicon-Photonic Networks for Emerging Computing Platforms, Luca Carloni, Columbia University, USA

Gala Dinner for Organization Committee and Invited Speakers
Day 2: June 26th
9:00-10:00

10:00-10:15 10:15-12:15











12:15-13:15
13:15-15:15











15:15-15:30
15:30-17:30


















Keynote session 3
Mentor or ST, France
Break
Session 4: Design Technologies for 3D
Design of a 3 layer 3D IC-stack including WideIO and a 3D-NoC : Design Flow and Perspectives, Pascal Vivet, LETI, Grenoble, France

Ravi Varadarajan, Atrenta, USA

3D Packaging Driving the Need for Multi-Form-Factor, Path Finding Solutions, John Park, Mentor Graphics

Nicolas Peltier, Docea

A Co-Design Methodology for 2.5D IC's, Tokunaga Shinya, STARC, Japan

Lunch
Session 5: Heterogeneous Integration
Gilles Simon, LETI, Grenoble, France

"Voltage Droop and Thermal Constraint Driven Optimization of 3D Power Delivery Networks", Aida Todri, LIRMM, Montpellier, France

Design of 3D specific Systems, Paul Franzon, NSCU, USA

Marc Duranton, LIST

Andreas Wilde, Fraunhofer Institute, Germany
Break
Panel: Who needs 3D?
Organizer: Yuan Xie, Pennsylvania State University, USA
Attendees: TSMC, STE, ST, E2S, GSA, Mentor Graphics

June 27th - D43D Tutorial Day

9:00-10:30

10:30-12:00

12:00-13:00
13:00-14:30
14:30-16:00
Modeling and Cooling Methodologies for Thermal-Aware Design of 3D ICs, Arvind Sridhar, EPFL, Switzerland
Efficient Thermal Management Strategies for 3D Stacked Multicore Systems, Ayse C. Coskun, Boston Univ., USA
Lunch break
"Main Challenges & key Technologies for 3D Integration, David henry, CEA-LETI, Grenoble, France
"Challenges and Opportunities of 3-D IC System architecture and design", Sean Lee, Georgia Institute of Technology, USA
Location and Access
Movenpick Hotel Lausanne
4, Avenue de Rhodanie
1006 Lausanne
Switzerland

Phone:+41 21 612 7 612
Fax:+41 21 612 7 611
E-mail: hotel.lausanne@moevenpick.com

This external link will show you how to access the Hotel

By car: take direction Lausanne Sud/Lausanne South on the A1 and drive straight to Lausanne-Ouchy.
The Hotel is located 1.5 km from the highway exit.

By train: Take the direct train service from Geneva/Bern and Zurich to Lausanne.
From Lausanne railway station, take a taxi or the M2 metro to Ouchy.
The M2 metro stops a few meters from the hotel.


Sponsors
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