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Previous editions
Focus
3-D ICs enable dramatically improved performances at a much lower cost than new leading-edge CMOS technology below 32 nm transistor fabrication. The success of these new ICs depends on the availability of new methodologies and skills that are required to achieve acceptable design quality and productivity. This workshop brings together key actors from semiconductor companies, system design houses and EDA industry to build a vision of the next step in 3D integrated ICs design. Topics addressed are: Applications requiring 3D, interconnect architectures and thermal management for 3D ICs, application partitioning, floor planning for 3D architectures, modeling, characterization and testing for 3D ICs.
Content
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Registration
Registration
Organization Committee

General Chairs:
Marc Belleville, CEA-LETI
Vasileios Pavlidis, EPFL

Program Chairs:
Alexandre Valentian, CEA-LETI
Yann Guillou, ST-Ericsson
Martino Ruggiero, EPFL





Tutorial Chairs:
Denis Dutoit, CEA-LETI
Yusuf Leblebici, EPFL
John R. Thome, EPFL

Organisation Chairs:
Ahmed Jerraya, CEA-LETI
David Atienza, EPFL
Giovanni De Micheli, EPFL

Website Chair:
Rodolphe Buret, EPFL
Downloads

Download here the PDF version of the D43D flyer Program (pdf)


Final Program
Day 1: June 29th
09:15-09:30 Opening: Marc Belleville
09:30-10:30
  • Session 1 - Design & Packaging for 3D IC - Chair: Marc Belleville
  • TSV Redundancy Scheme for 3D IC, Steve Lin, National Tsing Hua University
  • 3D IC Standardization: Assembly Point of View, Yishao Lai, ASE Group*
10:30-11:00 Break
11:00-12:30
  • Session 2: Design Tools - Chair: Ahmed Jerraya
  • Damien Riquet, ST
  • Claudia Rusu, Atrenta
  • Power and thermal analysis in IC design: from 2D to 3D,Sylvain Kaiser, Docea Power
  • Lisa McIlrath, R3Logic
  • Jean-François Lepere, Cadence
12:30-14:00 Lunch
14:00-15:30
  • Session 3: Thermal Cooling Technologies - Chair: Haykel Ben Jamaa
  • Sachin Spatnekar, Univerity of Minnesota
  • How to take profit of 3D IC integration, Yves Leduc, Texas Instruments
  • Modeling Issues for Thermal TSVs, Hu Xu, EPFL
15:30-16:00 Break
16:00-18:00
  • Session 4: Interposer and Manufacturing Chain - Chair: Alexandre Valentian
  • Reliability and Variability in TSV-based 3D-IC Designs, David Pan, U. Texas Austin
  • Process for Interposer, Nicolas Sillon, CEA-LETI
  • Silicon Interposers and Beyond : A System Design View, Matthew Hogan, Mentor Graphics
  • A 3D Asynchronous Network-on-Chip Architecture including Testability and Fault Tolerance, Pascal Vivet, CEA-LETI
19:00 Gala Dinner




Day 2: June 30th
09:00-10:30
  • Keynote session - Chair: Marc Belleville
  • Heterogeneous Integration, Jean-François Carpentier, ST
  • 3D Integration from the Viewpoint of High-End Server Systems, Thomas Brunschwiler, IBM Research, Zurich
10:30-11:00 Break
11:00-12:30
  • Session 5: 3D For Computing - Chair: Didier Lattard
  • Integrating Emerging Memory on Top of CMP: Opportunities and Challenge, Prof Li, NYU Poly
  • Yuan Xie, The Pennsylvania State University
  • Less TSVs in 3D chips through Asynchronous Serialization, Frederic Petrot, TIMA
12:30-14:00 Lunch
14:00-15:30
  • Session 6: Applications and Technologies for 3D Chips - Chair: Vasileios Pavlidis
  • Breaking the Bandwidth Wall in Servers with Multi-Gigabyte On-Chip Caches, Babak Falsafi, EPFL
  • 3D memory architecture, Koji Inoue, Kyushu University
  • Georg Kimmich, STE
15:30-16:00 Break
16:00-17:30
  • Panel: 3D TSV technologies business expectations and outlooks
  • organised by Yann Guillou, STE Speakers from: Jacky Seiller, Amkor, Mickael Rien, ARM, Jason Phua, Global Foundries, Global Foundries, Herb Reiter, eda2asic Consulting & Global Semiconductor Association, Christophe Zinck, Yole




  • * to be confirmed
Day 3: July 1st - D43D Tutorial Day (Tutorial Chairs: Denis Dutoit, Yusuf Leblebici, John R. Thome)
9:30-10:30 Patrick Leduc, LETI, 3D Integration and Manufacturing
10:30-11:00 break
11:00-12:30 Sachin S. Sapatnekar, University of Minnesota, 3D Design tools
12:30-14:00 Lunch break
14:00-15:30 David Atienza, EPFL, Thermal modeling and analysis
15:30-16:00 break
16:00-17:30 Yuan Xie, PSU, 3D Applications for Computing
Location and Access
CEA/LETI/DCIS MINATEC
17 rue des Martyrs
Cedex 9, Grenoble 38054 (FRANCE)

Location of CEA-LETI with googlemaps
Details of access to the MINATEC site are available on this page: MINATEC access
You can download a map of situation in pdf format: map
Sponsors
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